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devices:lenovo_t500

Information

  • Lenovo T500 laptop

Resources

Coreboot

Issues

  • When booting Ubuntu 18.10, there's a gfx error initially; type help and press Enter to boot
  • :!: Be absolute certain to update the BIOS and ECP from the Lenovo Vendor BIOS with an attached rear-battery, as there is no way as of 2019/01/25 to update the ECP from Coreboot

RAM

Incompatible

Compatible

Dependencies

Ubuntu Server

  • 18.04.1
sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev python-minimal

Download Source

Coreboot

cd ~ && mkdir -p ~/'Projects' && rm -Rf ~/'Projects/coreboot/src' && git clone --branch 'master' --depth '1' --recurse-submodules 'https://review.coreboot.org/coreboot.git' ~/'Projects/coreboot/src' && sync

Libreboot

cd ~ && mkdir -p ~/'Projects' && rm -Rf ~/'Projects/libreboot/src' && git clone --branch 'master' --depth '1' --recurse-submodules 'https://notabug.org/libreboot/libreboot.git' ~/'Projects/libreboot/src' && sync

ich9gen

Notes

Compile

cd ~/'Projects/libreboot/src/resources/utilities/ich9deblob' && make clean && make jobs='16' && sync

Generate

  • :!: Change x to the on-board Ethernet MAC address formatted as XX:XX:XX:XX:XX:XX 5)
cd ~/'Projects/libreboot/src/resources/utilities/ich9deblob' && ~/'Projects/libreboot/src/resources/utilities/ich9deblob/ich9gen' --macaddress 'x'

Move

  • This copies the generated ich9fdgbe_4m.bin to the necessary folder for Coreboot
  • The T500 uses the same board build as the T400 in Coreboot currently, hence the t400 mainboard name
  • :!: If the BIOS chip is a different size other than 4096KB, change this
mkdir -p ~/'Projects/coreboot/src/3rdparty/blobs/mainboard/lenovo/t400' && mv ~/'Projects/libreboot/src/resources/utilities/ich9deblob/ich9fdgbe_4m.bin' ~/'Projects/coreboot/src/3rdparty/blobs/mainboard/lenovo/t400/descriptor.bin' && ls ~/'Projects/coreboot/src/3rdparty/blobs/mainboard/lenovo/t400/descriptor.bin' && cd ~ && rm -Rf ~/'Projects/libreboot' && sync

Build Toolchain

cd ~/'Projects/coreboot/src' && make 'crossgcc-clean' && make 'crossgcc-i386' CPUS='16'

Settings

  • Last updated: 2019/07/06
  • Mainboard vendor: Lenovo
  • Mainboard model: ThinkPad T500
  • :!: ROM chip size: 4096 KB (4MB)
  • Local version string: Spinesnap
  • [*] Use CMOS for configuration values
  • [*] Load default configuration values into CMOS on each boot
  • [ ] Compress ramstage with LZMA
  • [ ] Include the coreboot .config file into the ROM image
  • [ ] Create a table of timestamps collected during boot
  • [ ] Enable VMX for virtualization
  • [ ] Set IA32_FEATURE_CONTROL lock bit
  • Include CPU microcode in CBFS: Do not include microcode updates
  • [*] Add Intel descriptor.bin file 6)
  • Display → Framebuffer mode: Linear “high-resolution” framebuffer
  • [*] Enable PCIe Common Clock
  • [*] Enable PCIe ASPM
  • [*] Enable PCIe Clock Power Management
  • [*] Enable PCIe ASPM L1 SubState
  • [ ] Serial port on SuperIO
  • [ ] Support Intel PCI-e WiFi adapters
  • [*] Always clear all DRAM on regular boot
  • [ ] Send console output to a CBMEM buffer
  • Default console log level: 0: EMERG
  • [*] Don't show any POST codes
  • SeaBIOS version: master
  • [*] Hardware init during option ROM execution
  • SeaBIOS debug level (verbosity): 0
cd ~/'Projects/coreboot/src' && make 'distclean' && make 'nconfig' && sync

Query

  • Presents config options that are changed from defaults
  • Last updated: 2019/07/06
cd ~/'Projects/coreboot/src' && make 'savedefconfig' && nano ~/'Projects/coreboot/src/defconfig'
CONFIG_LOCALVERSION="Spinesnap"
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
# CONFIG_COMPRESS_RAMSTAGE is not set
# CONFIG_INCLUDE_CONFIG_FILE is not set
# CONFIG_COLLECT_TIMESTAMPS is not set
CONFIG_VENDOR_LENOVO=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_BOARD_LENOVO_T500=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_CLK_PM=y
# CONFIG_CONSOLE_CBMEM is not set
# CONFIG_ENABLE_VMX is not set
# CONFIG_SET_IA32_FC_LOCK_BIT is not set
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_NO_POST=y
CONFIG_SEABIOS_MASTER=y
CONFIG_SEABIOS_THREAD_OPTIONROMS=y
CONFIG_SEABIOS_DEBUG_LEVEL=0

CMOS Settings

  • Last updated: 2019/02/12
nano ~/'Projects/coreboot/src/src/mainboard/lenovo/t400/cmos.default'
gfx_uma_size=352M

Make

cd ~/'Projects/coreboot/src' && make clean && make && sync

Finalize

mkdir -p ~/'coreboot-bin' && mv ~/'Projects/coreboot/src/build/coreboot.rom' ~/'coreboot-bin/T500-coreboot-'$(date +%Y-%m-%d)'.rom' && sync

Virtual Machine

  • :!: Change X to the VM instance's IP address
scp 192.168.122.X:~/coreboot-bin/*.rom ~/Downloads

Flash

  • :!: The initial flash must be done by an external programmer 7)
sync && sudo flashrom --programmer 'internal:laptop=force_I_want_a_brick' --chip 'MX25L3205D/MX25L3208D' --write ~/'Downloads/T500-coreboot-'*'.rom'
2)
incompatible with Coreboot 2018/12 (unknown day), incompatible with Libreboot 20160907, untested with Lenovo Vendor BIOS 3.26
3)
compatible with Coreboot 2019/01/25, untested with Libreboot, untested with Lenovo Vendor BIOS 3.26
4)
Intel Management Engine
5)
this should look like --macaddress XX:XX:XX:XX:XX:XX
6)
keep 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin path
7)
Running the Lenovo vendor BIOS through ifdtool with the --unlock flag does not unlock the chip; so any re-flash to the Lenovo vendor BIOS will require an external programmer to flash different firmware
devices/lenovo_t500.txt · Last modified: 2019/07/06 09:33 by Sean Rhone